In-memory processing on the spintronic cram: From hardware design to application mapping

Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jian Ping Wang, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

The Computational Random Access Memory (CRAM) is a platform that makes a small modification to a standard spintronics-based memory array to organically enable logic operations within the array. CRAM provides a true in-memory computational platform that can perform computations within the memory array, as against other methods that send computational tasks to a separate processor module or a near-memory module at the periphery of the memory array. This paper describes how the CRAM structure can be built and utilized, accounting for considerations at the device, gate, and functional levels. Techniques for constructing fundamental gates are first overviewed, accounting for electrical and noise margin considerations. Next, these logic operations are composed to schedule operations in the array that implement basic arithmetic operations such as addition and multiplication. These methods are then demonstrated on 2D convolution with multibit data, and a binary neural inference engine. The performance of the CRAM is analyzed on near-Term and longer-Term spintronic device technologies. Significant improvements in energy and execution time for the CRAM-based implementation over a near-memory processing system are demonstrated, and can be attributed to the ability of CRAM to overcome the memory access bottleneck, and to provide high levels of parallelism to the computation.

Original languageEnglish (US)
Article number8416761
Pages (from-to)1159-1173
Number of pages15
JournalIEEE Transactions on Computers
Volume68
Issue number8
DOIs
StatePublished - Aug 1 2019

Bibliographical note

Funding Information:
This work was supported in part by US National Science Foundation SPX Award CCF-1725420, and by C-SPIN, one of the six SRC STARnet Centers, sponsored by MARCO and DARPA.

Keywords

  • STT-MRAM
  • Spintronics
  • in-memory computing
  • memory bottleneck
  • neuromorphic computing
  • nonvolatile memory

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