Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

Drew C. Ness, Christian J. Hescott, David J Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15x variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level.

Original languageEnglish (US)
Title of host publication2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
PublisherIEEE Computer Society
Pages46-53
Number of pages8
ISBN (Print)9781424417919
DOIs
StatePublished - Jan 1 2007
Event2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH - San Jose, CA, United States
Duration: Oct 21 2007Oct 22 2007

Publication series

Name2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH

Other

Other2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
CountryUnited States
CitySan Jose, CA
Period10/21/0710/22/07

Keywords

  • Circuit level reliability
  • Plackett and Burman design
  • Single event upset (SEU)
  • Soft-error rate (SER)

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