Improved Bipolar Transistor Performance in a VLSI CMOS Process

C. S. Yue; C. C. Huang; J. W. Schrankler; N. F. Pu; G. D. Kirchner; C. Rahn

doi:10.1109/EDL.1983.25738

Improved Bipolar Transistor Performance in a VLSI CMOS Process

C. S. Yue, C. C. Huang, J. W. Schrankler, N. F. Pu, G. D. Kirchner, C. Rahn

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Abstract

Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector–emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf = 100, BVCE0 = 9.0 V, and BVCB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.

Original language	English (US)
Pages (from-to)	294-296
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	4
Issue number	8
DOIs	https://doi.org/10.1109/EDL.1983.25738
State	Published - Aug 1983

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10.1109/EDL.1983.25738

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title = "Improved Bipolar Transistor Performance in a VLSI CMOS Process",

abstract = "Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector–emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf = 100, BVCE0 = 9.0 V, and BVCB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.",

author = "Yue, \{C. S.\} and Huang, \{C. C.\} and Schrankler, \{J. W.\} and Pu, \{N. F.\} and Kirchner, \{G. D.\} and C. Rahn",

year = "1983",

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AU - Yue, C. S.

AU - Huang, C. C.

AU - Schrankler, J. W.

AU - Pu, N. F.

AU - Kirchner, G. D.

AU - Rahn, C.

PY - 1983/8

Y1 - 1983/8

N2 - Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector–emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf = 100, BVCE0 = 9.0 V, and BVCB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.

AB - Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector–emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf = 100, BVCE0 = 9.0 V, and BVCB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 8

ER -

Improved Bipolar Transistor Performance in a VLSI CMOS Process

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