Improved Bipolar Transistor Performance in a VLSI CMOS Process

C. S. Yue, C. C. Huang, J. W. Schrankler, N. F. Pu, G. D. Kirchner, C. Rahn

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector–emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf = 100, BVCE0 = 9.0 V, and BVCB0 = 23 V can be easily fabricated on this scaled VLSI CMOS process.

Original languageEnglish (US)
Pages (from-to)294-296
Number of pages3
JournalIEEE Electron Device Letters
Issue number8
StatePublished - Aug 1983


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