Improved application of surge capacitors for TRV reduction when clearing capacitor bank faults

Pratap G. Mysore, Bruce A. Mork, Himanshu J. Bahirat

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

Current-limiting reactors are placed in series with capacitor banks to limit the rate of rise of current to the values specified in the circuit breaker (CB) standards. But this arrangement has created capacitor bank failures when attempting to clear faults in between the reactor and the capacitor bank. After detailed analyses of failures, solutions have been proposed by researchers: 1) Add a surge capacitor to ground on the capacitor bank side of the breaker and 2) add a surge capacitor across the reactor. These surge capacitors are sized based on the stray capacitances of the bus, the reactor, the circuit breaker, and on the maximum-available fault current at the substation. This paper presents a simplified means of sizing the surge capacitors for method 2), based only on the CB's interrupting current rating and reactor size. This eliminates the need for and uncertainty of stray capacitance values. Also, the design does not need to be revisited when grid enhancements increase the available fault current at a substation. A standard surge protection package, which can also be applied to existing installations, is proposed. This new approach has been verified with studies using Electromagnetic Transients Program/Alternative Transients Program.

Original languageEnglish (US)
Article number5556036
Pages (from-to)2489-2495
Number of pages7
JournalIEEE Transactions on Power Delivery
Volume25
Issue number4
DOIs
StatePublished - Oct 2010
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received April 15, 2009; revised February 27, 2010. Date of publication August 23, 2010; date of current version September 22, 2010. This work was supported by Xcel Energy, Inc., Minneapolis, MN. Paper no. TPWRD-00874-2008. P. G. Mysore is with Xcel Energy, Inc., Minneapolis, MN 55401 USA (e-mail: Pratap.G.Mysore@xcelenergy.com). B. A. Mork and H. J. Bahirat are with the Department of Electrical Engineering, Michigan Technological University, Houghton, MI 49931 USA (e-mail: bamork@mtu.edu; hjbahira@mtu.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPWRD.2010.2050605

Keywords

  • Current limiting reactor
  • inrush currents
  • outrush currents
  • transient recovery voltage

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