The effects of gate structure design on RF performance of strained-Si/SiGe nMODFETs are studied using device simulation and experiments. It is found that while gate resistance only affects fmax, fringing gate capacitance can have a significant impact on both fT and fmax, indicating that the physical gate structure has to be optimized for any specific application. The experiments suggest that low-ic material is needed as sidewall spacer (if any) and passivation for reducing fringing gate capacitance. Furthermore, the simulations show that if low gate resistance can be achieved by using a multi-finger geometry, a rectangular-shaped gate should be used in order to reduce fringing gate capacitance. If not, a T-gate should be used to reduce gate resistance for high fmax.
|Title of host publication
|SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2003
|2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 - Boston, United States
Duration: Sep 3 2003 → Sep 5 2003
|International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
|2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003
|9/3/03 → 9/5/03
Bibliographical notePublisher Copyright:
© 2003 IEEE.
- CMOS technology
- Germanium silicon alloys
- Immune system
- Radio frequency
- Silicon germanium