Impact on performance, power, area and wirelength using electromigration-aware cells

Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis; Sachin S Sapatnekar

doi:10.1109/ICECS.2015.7440266

Impact on performance, power, area and wirelength using electromigration-aware cells

Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Electromigration (EM) is one of the critical reliability concerns, causing shorts and opens in metal interconnects, leading to interconnection failures and decreasing the time to failure (TTF) of the chip. In this way, EM-aware optimization is an important step of high reliability circuit design. Usually EM optimizations are applied on the power network and signals connecting cells. Otherwise, the internal wires of the cells are also affected by EM and they also have to be optimized to be EM-aware. One way to reduce the EM effects inside of the cells is placing the output pins at positions that reduce the EM. The critical pin positions that produces high current densities and consequently more EM are avoided, making the cells EM-aware. Thereby, in this work we are presenting the impact on area, delay, power and wirelength when different amounts of cells in a circuit are optimized to be EM-aware. We are using the NANGATE 45nm cell library scaling down to 22nm considering SPICE PTM models for simulation.

Original language	English (US)
Title of host publication	2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	129-132
Number of pages	4
ISBN (Electronic)	9781509002467
DOIs	https://doi.org/10.1109/ICECS.2015.7440266
State	Published - Mar 23 2016
Event	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 - Cairo, Egypt Duration: Dec 6 2015 → Dec 9 2015

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	2016-March

Other

Other	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Country/Territory	Egypt
City	Cairo
Period	12/6/15 → 12/9/15

Bibliographical note

Funding Information:
This work is partially supported by Brazilian National Council for Scientific and Technological Development (CNPq - Brazil) and Coordination for the Improvement of Higher Education Personnel (CAPES).

Publisher Copyright:
© 2015 IEEE.

Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.

Publisher link

10.1109/ICECS.2015.7440266

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Posser, G., Mishra, V., Jain, P., Reis, R., & Sapatnekar, S. S. (2016). Impact on performance, power, area and wirelength using electromigration-aware cells. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 (pp. 129-132). [7440266] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2015.7440266

Impact on performance, power, area and wirelength using electromigration-aware cells. / Posser, Gracieli; Mishra, Vivek; Jain, Palkesh et al.

2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 129-132 7440266 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Posser, G, Mishra, V, Jain, P, Reis, R & Sapatnekar, SS 2016, Impact on performance, power, area and wirelength using electromigration-aware cells. in 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015., 7440266, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 2016-March, Institute of Electrical and Electronics Engineers Inc., pp. 129-132, IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, 12/6/15. https://doi.org/10.1109/ICECS.2015.7440266

Posser G, Mishra V, Jain P, Reis R, Sapatnekar SS. Impact on performance, power, area and wirelength using electromigration-aware cells. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 129-132. 7440266. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2015.7440266

Posser, Gracieli ; Mishra, Vivek ; Jain, Palkesh et al. / Impact on performance, power, area and wirelength using electromigration-aware cells. 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 129-132 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

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abstract = "Electromigration (EM) is one of the critical reliability concerns, causing shorts and opens in metal interconnects, leading to interconnection failures and decreasing the time to failure (TTF) of the chip. In this way, EM-aware optimization is an important step of high reliability circuit design. Usually EM optimizations are applied on the power network and signals connecting cells. Otherwise, the internal wires of the cells are also affected by EM and they also have to be optimized to be EM-aware. One way to reduce the EM effects inside of the cells is placing the output pins at positions that reduce the EM. The critical pin positions that produces high current densities and consequently more EM are avoided, making the cells EM-aware. Thereby, in this work we are presenting the impact on area, delay, power and wirelength when different amounts of cells in a circuit are optimized to be EM-aware. We are using the NANGATE 45nm cell library scaling down to 22nm considering SPICE PTM models for simulation.",

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N1 - Funding Information: This work is partially supported by Brazilian National Council for Scientific and Technological Development (CNPq - Brazil) and Coordination for the Improvement of Higher Education Personnel (CAPES). Publisher Copyright: © 2015 IEEE. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.

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N2 - Electromigration (EM) is one of the critical reliability concerns, causing shorts and opens in metal interconnects, leading to interconnection failures and decreasing the time to failure (TTF) of the chip. In this way, EM-aware optimization is an important step of high reliability circuit design. Usually EM optimizations are applied on the power network and signals connecting cells. Otherwise, the internal wires of the cells are also affected by EM and they also have to be optimized to be EM-aware. One way to reduce the EM effects inside of the cells is placing the output pins at positions that reduce the EM. The critical pin positions that produces high current densities and consequently more EM are avoided, making the cells EM-aware. Thereby, in this work we are presenting the impact on area, delay, power and wirelength when different amounts of cells in a circuit are optimized to be EM-aware. We are using the NANGATE 45nm cell library scaling down to 22nm considering SPICE PTM models for simulation.

AB - Electromigration (EM) is one of the critical reliability concerns, causing shorts and opens in metal interconnects, leading to interconnection failures and decreasing the time to failure (TTF) of the chip. In this way, EM-aware optimization is an important step of high reliability circuit design. Usually EM optimizations are applied on the power network and signals connecting cells. Otherwise, the internal wires of the cells are also affected by EM and they also have to be optimized to be EM-aware. One way to reduce the EM effects inside of the cells is placing the output pins at positions that reduce the EM. The critical pin positions that produces high current densities and consequently more EM are avoided, making the cells EM-aware. Thereby, in this work we are presenting the impact on area, delay, power and wirelength when different amounts of cells in a circuit are optimized to be EM-aware. We are using the NANGATE 45nm cell library scaling down to 22nm considering SPICE PTM models for simulation.

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Impact on performance, power, area and wirelength using electromigration-aware cells

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