Electromigration (EM) is one of the critical reliability concerns, causing shorts and opens in metal interconnects, leading to interconnection failures and decreasing the time to failure (TTF) of the chip. In this way, EM-aware optimization is an important step of high reliability circuit design. Usually EM optimizations are applied on the power network and signals connecting cells. Otherwise, the internal wires of the cells are also affected by EM and they also have to be optimized to be EM-aware. One way to reduce the EM effects inside of the cells is placing the output pins at positions that reduce the EM. The critical pin positions that produces high current densities and consequently more EM are avoided, making the cells EM-aware. Thereby, in this work we are presenting the impact on area, delay, power and wirelength when different amounts of cells in a circuit are optimized to be EM-aware. We are using the NANGATE 45nm cell library scaling down to 22nm considering SPICE PTM models for simulation.
|Original language||English (US)|
|Title of host publication||2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - Mar 23 2016|
|Event||IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 - Cairo, Egypt|
Duration: Dec 6 2015 → Dec 9 2015
|Name||Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems|
|Other||IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015|
|Period||12/6/15 → 12/9/15|
Bibliographical noteFunding Information:
This work is partially supported by Brazilian National Council for Scientific and Technological Development (CNPq - Brazil) and Coordination for the Improvement of Higher Education Personnel (CAPES).