Impact of temporal transistor variations on circuit reliability

Runsheng Wang; Yu Cao

doi:10.1109/ISCAS.2015.7169181

Impact of temporal transistor variations on circuit reliability

Runsheng Wang
, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.

Original language	English (US)
Title of host publication	2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2453-2456
Number of pages	4
ISBN (Electronic)	9781479983919
DOIs	https://doi.org/10.1109/ISCAS.2015.7169181
State	Published - Jul 27 2015
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal Duration: May 24 2015 → May 27 2015

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2015-July
ISSN (Print)	0271-4310

Other

Other	IEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	5/24/15 → 5/27/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

bias temperature instability (BTI)
circuit reliability
random telegraph noise (RTN)
temporal variation

Publisher link

10.1109/ISCAS.2015.7169181

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Wang, R., & Cao, Y. (2015). Impact of temporal transistor variations on circuit reliability. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 2453-2456). Article 7169181 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7169181

Impact of temporal transistor variations on circuit reliability. / Wang, Runsheng; Cao, Yu.
2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2453-2456 7169181 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, R & Cao, Y 2015, Impact of temporal transistor variations on circuit reliability. in 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015., 7169181, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 2453-2456, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, 5/24/15. https://doi.org/10.1109/ISCAS.2015.7169181

@inproceedings{c7df98f0289b4911a6f96db3a0d3571c,

title = "Impact of temporal transistor variations on circuit reliability",

abstract = "With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.",

keywords = "bias temperature instability (BTI), circuit reliability, random telegraph noise (RTN), temporal variation",

author = "Runsheng Wang and Yu Cao",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE International Symposium on Circuits and Systems, ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

year = "2015",

month = jul,

day = "27",

doi = "10.1109/ISCAS.2015.7169181",

language = "English (US)",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2453--2456",

booktitle = "2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015",

}

TY - GEN

T1 - Impact of temporal transistor variations on circuit reliability

AU - Wang, Runsheng

AU - Cao, Yu

PY - 2015/7/27

Y1 - 2015/7/27

N2 - With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.

AB - With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness.

KW - bias temperature instability (BTI)

KW - circuit reliability

KW - random telegraph noise (RTN)

KW - temporal variation

UR - https://www.scopus.com/pages/publications/84946196830

UR - https://www.scopus.com/pages/publications/84946196830#tab=citedBy

U2 - 10.1109/ISCAS.2015.7169181

DO - 10.1109/ISCAS.2015.7169181

M3 - Conference contribution

AN - SCOPUS:84946196830

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 2453

EP - 2456

BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015

Y2 - 24 May 2015 through 27 May 2015

ER -

Impact of temporal transistor variations on circuit reliability

Abstract

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