Abstract
On-chip interconnect exhibits clear frequency-dependence in both resistance and inductance. A compact ladder circuit model is developed to capture this behavior, and we examine its impact on digital and RF circuit design. It is demonstrated that the use of DC values for R and L is sufficient for delay analysis, but RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
| Editors | John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 438-442 |
| Number of pages | 5 |
| ISBN (Electronic) | 0780374940 |
| DOIs | |
| State | Published - 2002 |
| Externally published | Yes |
| Event | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002 |
Publication series
| Name | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
|---|---|
| Volume | 2002-January |
| ISSN (Print) | 1063-0988 |
Conference
| Conference | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
|---|---|
| Country/Territory | United States |
| City | Rochester |
| Period | 9/25/02 → 9/28/02 |
Bibliographical note
Publisher Copyright:© 2002 IEEE.