TY - GEN
T1 - Impact of architecture choices on DSP circuits
AU - Parhi, K. K.
PY - 1992/1/1
Y1 - 1992/1/1
N2 - Selection of proper architecture and implementation styles can strongly influence the performance of dedicated VLSI DSP circuits. The impact of architecture choices is illustrated by considering a number of representative signal processing examples and a few general architecture transformation techniques. It is shown that algorithm transformation techniques such as look-ahead computation can create concurrency in nonconcurrent recursive signal processing algorithms, and that inherently new signal processing algorithms are processed with concurrency. This leads to pipelined algorithm topologies without any hardware overhead. To illustrate the impact of the implementation styles, it is shown that the internal redundant number system can lead to more efficient realization of multipliers and adders. Using systematic folding and unfolding techniques, digit-serial architectures with no restrictions on the digit size can be described. All of these architectural techniques can increase the performance of DSP circuits.
AB - Selection of proper architecture and implementation styles can strongly influence the performance of dedicated VLSI DSP circuits. The impact of architecture choices is illustrated by considering a number of representative signal processing examples and a few general architecture transformation techniques. It is shown that algorithm transformation techniques such as look-ahead computation can create concurrency in nonconcurrent recursive signal processing algorithms, and that inherently new signal processing algorithms are processed with concurrency. This leads to pipelined algorithm topologies without any hardware overhead. To illustrate the impact of the implementation styles, it is shown that the internal redundant number system can lead to more efficient realization of multipliers and adders. Using systematic folding and unfolding techniques, digit-serial architectures with no restrictions on the digit size can be described. All of these architectural techniques can increase the performance of DSP circuits.
UR - http://www.scopus.com/inward/record.url?scp=30244552634&partnerID=8YFLogxK
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U2 - 10.1109/TENCON.1992.271863
DO - 10.1109/TENCON.1992.271863
M3 - Conference contribution
AN - SCOPUS:30244552634
T3 - IEEE Region 10 Annual International Conference, Proceedings/TENCON
SP - 784
EP - 788
BT - TENCON 1992 - Technology Enabling Tomorrow
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE Region 10 International Conference on Technology Enabling Tomorrow: Computers, Communications and Automation towards the 21st Century, TENCON 1992
Y2 - 11 November 1992 through 13 November 1992
ER -