In the center of our work lies an FPGA implementation of an iterative image restoration algorithm. Our work presents an initial analysis of the algorithm as well as modifications made on the algorithm during the adaptation onto reconfigurable platform. We are presenting our hardware design for the image restoration algorithm and our estimations on the performance of the FPGA implementation. Our results show that the speedup gained for practical systems varies between 6.5 and 10.2 for different images. In this paper we are also proposing and evaluating a statistical method for analysis of images subject to restoration to gain insight into the convergence time of the restoration algorithm. Based on this we explored a image partitioning strategy using this statistical analysis.
|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation|
|State||Published - Dec 1 2000|
|Event||2000 IEEE Workshop on Signal Processing Systems (SIPS 2000) - Lafayette, LA, USA|
Duration: Oct 11 2000 → Oct 13 2000