iDEAS: A delay estimator and transistor sizing tool for CMOS circuits

Sachin S. Sapatnekar, Vasant B. Rao

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

The iDEAS algorithm incorporates a delay estimator that uses both the rise and fall delay to find the critical path through a given circuit. A method that attempts to minimize the area-delay product of the circuit is developed to optimize the sizes of transistors along the critical path. These two steps are repeated until the specified delay and area requirements for the circuit are met. This algorithm is designed for use on combinational circuits, and is also applicable to clocked circuits, where each stage of the clocked circuit is combinational.

Original languageEnglish (US)
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Dec 1 1990
EventProceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA
Duration: May 13 1990May 16 1990

Fingerprint Dive into the research topics of 'iDEAS: A delay estimator and transistor sizing tool for CMOS circuits'. Together they form a unique fingerprint.

Cite this