Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs

Keyphrases

• Hardware Cost 100%
• DSP Applications 100%
• Truncated multiplier 100%
• Truncated multiplication 100%
• Unary 100%
• DSP System 66%
• Approximate multiplier 66%
• Low Energy 33%
• Evaluation Results 33%
• Basic Building Block 33%
• FIR Filter 33%
• Fast Fourier Transform 33%
• Power Consumption 33%
• Discrete Cosine Transform 33%
• Area Reduction 33%
• Xilinx 33%
• Encoding Method 33%
• Computing Methods 33%
• DSP Algorithms 33%
• Error Correction Mechanism 33%
• Resource Consumption 33%
• Fast Fourier 33%
• Fourier Cosine Transform 33%
• Two-dimensional Discrete Cosine Transform 33%
• FPGA Resources 33%
• Reduced Error 33%
• Unary Computing 33%
• Unary Encoding 33%

Computer Science

• Hardware Cost 100%
• Field Programmable Gate Arrays 100%
• Discrete Cosine Transform 66%
• Power Consumption 33%
• Building-Blocks 33%
• Fast Fourier Transform 33%
• Error Correction 33%
• Resource Consumption 33%
• Finite Impulse Response Filter 33%