Multipliers are the basic building blocks of modern DSP systems and contribute significantly to their overall performance. In many DSP systems, using truncated multipliers instead of full precision multipliers can keep the accuracy at a desirable level while significantly reducing FPGA resources, delay, and power consumption. Truncated multipliers are widely used to accelerate DSP applications such as filtering, fast Fourier, and discrete cosine transforms. In this paper we propose a novel low-cost, low energy, and highspeed truncated multiplier using a hybrid binary-unary encoding method. We take advantage of the unary computing method to exploit two error correction mechanisms in order to reduce error without adding to the hardware cost. The proposed multipliers outperform Xilinx LogiCORE IP in terms of hardware cost, and outperform state-of-the-art FPGA-specific approximate multipliers in terms of accuracy and hardware costs. The proposed approximate multipliers result in area reductions between 12% to 48% for 7- to 15-bit multipliers on average. We assess the performance of the proposed multipliers on an FIR filter, 2-D discrete cosine transform, and fast Fourier transform as three common DSP algorithms. The evaluation results show that these applications can deliver desirable performance using the proposed multipliers.
|Original language||English (US)|
|Journal||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD|
|State||Published - Nov 2 2020|
|Event||39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020 - Virtual, San Diego, United States|
Duration: Nov 2 2020 → Nov 5 2020
Bibliographical notePublisher Copyright:
© 2020 Association on Computer Machinery.
- Approximate Computing
- Truncated Multiplier
- Unary Computing