Hybrid binary-unary hardware accelerator

S. Rasoul Faraji, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the low area advantage comes at an exponential price in latency, making the area × delay cost unattractive. In this paper, we present a novel method which uses a hybrid binary / unary representation to perform computations. We first divide the input range into a few sub-regions, perform unary computations on each sub-region individually, and finally pack the outputs of all sub-regions back to compact binary. Moreover, we propose a synthesis methodology and a regression model to predict an optimal or sub-optimal design in the design space. The proposed method is especially well-suited to FPGAs due to the abundant availability of routing and flip-flop resources. To the best of our knowledge, we are the first to show a scalable method based on the principles of stochastic computing that can beat conventional binary in terms of a real cost, i.e., area×delay. Our method outperforms the binary and fully unary methods on a number of functions and on a common edge detection algorithm. In terms of area × delay cost, our cost is on average only 2.51% and 10.2% of the binary for 8- and 10-bit resolutions, respectively. These numbers are 2-3 orders of magnitude better than the results of traditional stochastic methods. Our method is not competitive with the binary method for high-resolution oscillating functions such as sin(15x).

Original languageEnglish (US)
Title of host publicationASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages210-215
Number of pages6
ISBN (Electronic)9781450360074
DOIs
StatePublished - Jan 21 2019
Event24th Asia and South Pacific Design Automation Conference, ASPDAC 2019 - Tokyo, Japan
Duration: Jan 21 2019Jan 24 2019

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other24th Asia and South Pacific Design Automation Conference, ASPDAC 2019
CountryJapan
CityTokyo
Period1/21/191/24/19

Fingerprint

Particle accelerators
Hardware
Costs
Flip flop circuits
Edge detection
Field programmable gate arrays (FPGA)
Availability

Keywords

  • Alternator Logic
  • Hardware accelerators
  • Hybrid computing system
  • Scaling Network
  • Unary computing system

Cite this

Rasoul Faraji, S., & Bazargan, K. (2019). Hybrid binary-unary hardware accelerator. In ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference (pp. 210-215). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3287624.3287706

Hybrid binary-unary hardware accelerator. / Rasoul Faraji, S.; Bazargan, Kia.

ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 210-215 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Rasoul Faraji, S & Bazargan, K 2019, Hybrid binary-unary hardware accelerator. in ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 210-215, 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, 1/21/19. https://doi.org/10.1145/3287624.3287706
Rasoul Faraji S, Bazargan K. Hybrid binary-unary hardware accelerator. In ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 210-215. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1145/3287624.3287706
Rasoul Faraji, S. ; Bazargan, Kia. / Hybrid binary-unary hardware accelerator. ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 210-215 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
@inproceedings{b3761e471cf04660ad4ead5ba86ce2b5,
title = "Hybrid binary-unary hardware accelerator",
abstract = "Stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the low area advantage comes at an exponential price in latency, making the area × delay cost unattractive. In this paper, we present a novel method which uses a hybrid binary / unary representation to perform computations. We first divide the input range into a few sub-regions, perform unary computations on each sub-region individually, and finally pack the outputs of all sub-regions back to compact binary. Moreover, we propose a synthesis methodology and a regression model to predict an optimal or sub-optimal design in the design space. The proposed method is especially well-suited to FPGAs due to the abundant availability of routing and flip-flop resources. To the best of our knowledge, we are the first to show a scalable method based on the principles of stochastic computing that can beat conventional binary in terms of a real cost, i.e., area×delay. Our method outperforms the binary and fully unary methods on a number of functions and on a common edge detection algorithm. In terms of area × delay cost, our cost is on average only 2.51{\%} and 10.2{\%} of the binary for 8- and 10-bit resolutions, respectively. These numbers are 2-3 orders of magnitude better than the results of traditional stochastic methods. Our method is not competitive with the binary method for high-resolution oscillating functions such as sin(15x).",
keywords = "Alternator Logic, Hardware accelerators, Hybrid computing system, Scaling Network, Unary computing system",
author = "{Rasoul Faraji}, S. and Kia Bazargan",
year = "2019",
month = "1",
day = "21",
doi = "10.1145/3287624.3287706",
language = "English (US)",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "210--215",
booktitle = "ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference",

}

TY - GEN

T1 - Hybrid binary-unary hardware accelerator

AU - Rasoul Faraji, S.

AU - Bazargan, Kia

PY - 2019/1/21

Y1 - 2019/1/21

N2 - Stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the low area advantage comes at an exponential price in latency, making the area × delay cost unattractive. In this paper, we present a novel method which uses a hybrid binary / unary representation to perform computations. We first divide the input range into a few sub-regions, perform unary computations on each sub-region individually, and finally pack the outputs of all sub-regions back to compact binary. Moreover, we propose a synthesis methodology and a regression model to predict an optimal or sub-optimal design in the design space. The proposed method is especially well-suited to FPGAs due to the abundant availability of routing and flip-flop resources. To the best of our knowledge, we are the first to show a scalable method based on the principles of stochastic computing that can beat conventional binary in terms of a real cost, i.e., area×delay. Our method outperforms the binary and fully unary methods on a number of functions and on a common edge detection algorithm. In terms of area × delay cost, our cost is on average only 2.51% and 10.2% of the binary for 8- and 10-bit resolutions, respectively. These numbers are 2-3 orders of magnitude better than the results of traditional stochastic methods. Our method is not competitive with the binary method for high-resolution oscillating functions such as sin(15x).

AB - Stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the low area advantage comes at an exponential price in latency, making the area × delay cost unattractive. In this paper, we present a novel method which uses a hybrid binary / unary representation to perform computations. We first divide the input range into a few sub-regions, perform unary computations on each sub-region individually, and finally pack the outputs of all sub-regions back to compact binary. Moreover, we propose a synthesis methodology and a regression model to predict an optimal or sub-optimal design in the design space. The proposed method is especially well-suited to FPGAs due to the abundant availability of routing and flip-flop resources. To the best of our knowledge, we are the first to show a scalable method based on the principles of stochastic computing that can beat conventional binary in terms of a real cost, i.e., area×delay. Our method outperforms the binary and fully unary methods on a number of functions and on a common edge detection algorithm. In terms of area × delay cost, our cost is on average only 2.51% and 10.2% of the binary for 8- and 10-bit resolutions, respectively. These numbers are 2-3 orders of magnitude better than the results of traditional stochastic methods. Our method is not competitive with the binary method for high-resolution oscillating functions such as sin(15x).

KW - Alternator Logic

KW - Hardware accelerators

KW - Hybrid computing system

KW - Scaling Network

KW - Unary computing system

UR - http://www.scopus.com/inward/record.url?scp=85061142373&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85061142373&partnerID=8YFLogxK

U2 - 10.1145/3287624.3287706

DO - 10.1145/3287624.3287706

M3 - Conference contribution

AN - SCOPUS:85061142373

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 210

EP - 215

BT - ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference

PB - Institute of Electrical and Electronics Engineers Inc.

ER -