HW/SW codesign incorporating edge delays using dynamic programming

K. Bhasyam, K. Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

We present an algorithm based on dynamic programming to perform the HW/SW partitioning and scheduling of a given task graph for minimum latency subject to resource constraint. The major contribution of this paper is to consider the edge communication delays in the dynamic programming solution of the problem. The algorithm has a polynomial run time complexity on trees. We also introduce a pruning technique to reduce the runtime of the worst-case scenario of directed acyclic graphs (DAGs). The algorithm has been implemented and the results are reported. A very fast quality heuristic is also proposed and implemented to provide good solutions in negligible run time.

Original languageEnglish (US)
Title of host publicationProceedings - Euromicro Symposium on Digital System Design, DSD 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages264-271
Number of pages8
ISBN (Electronic)0769520030, 9780769520032
DOIs
StatePublished - Jan 1 2003
EventEuromicro Symposium on Digital System Design, DSD 2003 - Belek-Antalya, Turkey
Duration: Sep 1 2003Sep 6 2003

Publication series

NameProceedings - Euromicro Symposium on Digital System Design, DSD 2003

Other

OtherEuromicro Symposium on Digital System Design, DSD 2003
CountryTurkey
CityBelek-Antalya
Period9/1/039/6/03

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