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HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Sparse matrix-vector multiplication (SpMV) is a fundamental operation in numerous applications such as scientific computing, machine learning, and graph analytics. While recent studies have made great progress in accelerating SpMV on HBM-equipped FPGAs, there are still multiple remaining challenges to efficiently accelerate imbalanced SpMV where the distribution of non-zeros in the sparse matrix is imbalanced across different rows. First, the imbalanced workload distribution among the parallel processing elements (PEs) leads to PE under-utilization and performance degradation. Second, the read-after-write dependency of the long-latency floating-point accumulation on the output vector causes pipeline stalls inside the PE, and existing scheduling solutions for balanced matrices no longer work effectively for imbalanced ones. Third, the memory access latency for the often overlooked input vector becomes a new performance bottleneck after the SpMV acceleration. To address the above challenges, in this work, we propose HiSpMV to accelerate imbalanced SpMV on HBM-equipped FPGAs. First, we design a hybrid row distribution network to enable both inter-row and intra-row distribution to achieve more balance. Second, we implement fully pipelined floating-point accumulation on the output vector using a combination of an adder tree and circular buffer. Third, we design a hybrid buffering technique to optimize the input vector loading from off-chip memory by dynamically switching between private partitioned buffers and shared ping-pong buffers. Lastly, we also developed an automation framework to automatically generate the optimized HiSpMV accelerator based on the user configurations. Experimental results demonstrate that HiSpMV achieves a geomean speedup of 13.7x (up to 60x) for highly imbalanced matrices, compared to state-of-the-art SpMV accelerator Serpens on the AMD-Xilinx Alveo U280 HBM-based FPGA. Compared to Intel MKL running on a 24-core Xeon Silver 4214 CPU, HiSpMV achieves a geomean speedup of 5.5x. Compared to cuSPARSE running on an NVIDIA 1080ti GPU, HiSpMV achieves a geomean of 2.1x better performance per watt.

Original languageEnglish (US)
Title of host publicationFPGA 2024 - Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
PublisherAssociation for Computing Machinery, Inc
Pages154-164
Number of pages11
ISBN (Electronic)9798400704185
DOIs
StatePublished - Apr 1 2024
Externally publishedYes
Event32nd ACM International Symposium on Field-Programmable Gate Arrays, FPGA 2024 - Monterey, United States
Duration: Mar 3 2024 → Mar 5 2024

Publication series

NameFPGA 2024 - Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

Conference

Conference32nd ACM International Symposium on Field-Programmable Gate Arrays, FPGA 2024
Country/TerritoryUnited States
CityMonterey
Period3/3/24 → 3/5/24

Bibliographical note

Publisher Copyright:
© 2024 ACM.

Keywords

  • fpga
  • hybrid buffering
  • hybrid design
  • spmv
  • workload imbalance

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