High-Throughput VLSI Architecture for FFT Computation

Chao Cheng, Keshab K Parhi

Research output: Contribution to journalArticle

54 Scopus citations

Abstract

In this brief, multi-path delay commutator structures are utilized to improve the throughput rate of radix-2 and radix-4 FFT computation by a factor of 2 to 4. Latency can also be reduced by a factor of 2 to 3. Compared with previous radix-2 and radix-4 FFT structures, the proposed high-throughput FFT with doubled throughput rate requires similar or even less hardware cost. Although split radix FFT design is more hardware efficient, the regular structure of proposed FFT structures are attractive for high throughput FFT design.

Original languageEnglish (US)
Pages (from-to)863-867
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume54
Issue number10
DOIs
StatePublished - Oct 2007

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Keywords

  • Fast Fourier transform
  • tensor product
  • very-large-scale integration

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