High throughput overlapped message passing for low density parity check codes

Yanni Chen, Keshab K. Parhi

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

In this paper, a systematic approach is proposed to develop high throughput decoder for structured (quasi-cyclic) low density parity check (LDPC) block codes. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by almost twice assuming dual-port memory is available.

Original languageEnglish (US)
Pages (from-to)245-248
Number of pages4
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
DOIs
StatePublished - Jul 28 2003
EventProceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States
Duration: Apr 28 2003Apr 29 2003

Keywords

  • High throughput
  • Low density parity check codes
  • Overlapped message passing

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