High throughput overlapped message passing for low density parity check codes

Yanni Chen; Keshab K. Parhi

doi:10.1142/9789812796769_0039

High throughput overlapped message passing for low density parity check codes

Yanni Chen, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

In this paper, a systematic approach is proposed to develop high throughput decoder for structured (quasi-cyclic) low density parity check (LDPC) block codes. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by almost twice assuming dual-port memory is available.

Original language	English (US)
Pages (from-to)	245-248
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
DOIs	https://doi.org/10.1142/9789812796769_0039
State	Published - Jul 28 2003
Event	Proceedings of the 2003 ACM Great Lakes Symposium on VLSI - Washington, DC, United States Duration: Apr 28 2003 → Apr 29 2003

Keywords

High throughput
Low density parity check codes
Overlapped message passing

Publisher link

10.1142/9789812796769_0039

Find It

Find It at U of M Libraries

Cite this

@article{4c03826236f041868b490a2e0acc5c6d,

title = "High throughput overlapped message passing for low density parity check codes",

abstract = "In this paper, a systematic approach is proposed to develop high throughput decoder for structured (quasi-cyclic) low density parity check (LDPC) block codes. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by almost twice assuming dual-port memory is available.",

keywords = "High throughput, Low density parity check codes, Overlapped message passing",

author = "Yanni Chen and Parhi, {Keshab K.}",

year = "2003",

month = jul,

day = "28",

doi = "10.1142/9789812796769_0039",

language = "English (US)",

pages = "245--248",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

note = "Proceedings of the 2003 ACM Great Lakes Symposium on VLSI ; Conference date: 28-04-2003 Through 29-04-2003",

}

TY - JOUR

T1 - High throughput overlapped message passing for low density parity check codes

AU - Chen, Yanni

AU - Parhi, Keshab K.

PY - 2003/7/28

Y1 - 2003/7/28

N2 - In this paper, a systematic approach is proposed to develop high throughput decoder for structured (quasi-cyclic) low density parity check (LDPC) block codes. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by almost twice assuming dual-port memory is available.

AB - In this paper, a systematic approach is proposed to develop high throughput decoder for structured (quasi-cyclic) low density parity check (LDPC) block codes. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by almost twice assuming dual-port memory is available.

KW - High throughput

KW - Low density parity check codes

KW - Overlapped message passing

UR - http://www.scopus.com/inward/record.url?scp=0037699705&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0037699705&partnerID=8YFLogxK

U2 - 10.1142/9789812796769_0039

DO - 10.1142/9789812796769_0039

M3 - Conference article

AN - SCOPUS:0037699705

SN - 1066-1395

SP - 245

EP - 248

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 2003 ACM Great Lakes Symposium on VLSI

Y2 - 28 April 2003 through 29 April 2003

ER -

High throughput overlapped message passing for low density parity check codes

Abstract

Keywords

Publisher link

Find It

Other files and links

Fingerprint

Cite this