High-speed VLSI implementation of 2-D discrete wavelet transform

Chao Cheng, Keshab K Parhi

Research output: Contribution to journalArticle

70 Scopus citations

Abstract

This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D DWT with computation time as low as N2/12 can be easily achieved for an N × N image with controlled increase of hardware cost. Compared with recently published 2-D DWT architectures with computation time of N2/3 and 2N2/3, the proposed designs can also save a large amount of multipliers and/or storage elements. It can also be used to implement those 2-D DWT traditionally suitable for lifting or flipping-based designs, such as (9,7) and (6,10) DWT. The throughput rate can be improved by a factor of 4 by the proposed approach, but the hardware cost increases by a factor of around 3. Furthermore, the proposed designs have very simple control signals, regular structures and 100% hardware utilization for continuous images.

Original languageEnglish (US)
Pages (from-to)393-403
Number of pages11
JournalIEEE Transactions on Signal Processing
Volume56
Issue number1
DOIs
StatePublished - Jan 1 2008

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Keywords

  • Cyclic convolution
  • Discrete wavelet transforms (DWTs)
  • Linear convolution
  • Very-large-scale integration (VLSI)

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