### Abstract

This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose new shifted remainder conditioning, and sign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2 W-1) to about W (where W is the word-length), when pipelined at the bit-level.

Original language | English (US) |
---|---|

Pages (from-to) | 177-198 |

Number of pages | 22 |

Journal | Journal of VLSI Signal Processing |

Volume | 4 |

Issue number | 2-3 |

DOIs | |

State | Published - May 1 1992 |

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### Cite this

*Journal of VLSI Signal Processing*,

*4*(2-3), 177-198. https://doi.org/10.1007/BF00925121

**High-speed VLSI arithmetic processor architectures using hybrid number representation.** / Srinivas, H. R.; Parhi, Keshab K.

Research output: Contribution to journal › Article

*Journal of VLSI Signal Processing*, vol. 4, no. 2-3, pp. 177-198. https://doi.org/10.1007/BF00925121

}

TY - JOUR

T1 - High-speed VLSI arithmetic processor architectures using hybrid number representation

AU - Srinivas, H. R.

AU - Parhi, Keshab K.

PY - 1992/5/1

Y1 - 1992/5/1

N2 - This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose new shifted remainder conditioning, and sign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2 W-1) to about W (where W is the word-length), when pipelined at the bit-level.

AB - This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose new shifted remainder conditioning, and sign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2 W-1) to about W (where W is the word-length), when pipelined at the bit-level.

UR - http://www.scopus.com/inward/record.url?scp=0001484299&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0001484299&partnerID=8YFLogxK

U2 - 10.1007/BF00925121

DO - 10.1007/BF00925121

M3 - Article

AN - SCOPUS:0001484299

VL - 4

SP - 177

EP - 198

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 2-3

ER -