High-speed VLSI architectures for the AES algorithm

Xinmiao Zhang, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

306 Scopus citations

Abstract

This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(24) are compared. In addition, an efficient key expansion architecture suitable for the subpipelined round units is also presented. Using the proposed architecture, a fully subpipelined encryptor with 7 substages in each round unit can achieve a throughput of 21.56 Gbps on a Xilinx XCV1000 e-8 bg560 device in non-feedback modes, which is faster and is 79% more efficient in terms of equivalent throughput/slice than the fastest previous FPGA implementation known to date.

Original languageEnglish (US)
Pages (from-to)957-967
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume12
Issue number9
DOIs
StatePublished - Sep 2004

Bibliographical note

Funding Information:
Manuscript received November 19, 2003; revised March 28, 2003. This work was supported by the Army Research Office under Grant DA/DAAD19-01-1-0705. The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: jennizh@ece.umn.edu; parhi@ece.umn.edu). Digital Object Identifier 10.1109/TVLSI.2004.832943

Keywords

  • Advanced Encryption Standard
  • Composite field arithmetic
  • Key expansion
  • Look-up table
  • Rijndael
  • Subpipelining
  • Substructure sharing

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