High-Speed VLSI Architectures for Huffman and Viterbi Decoders

Computer Science

• Parallel Architectures 100%
• Hardware Overhead 100%
• Logic Minimization 100%
• Very large-scale integration (VLSI) architecture 100%
• pipelined architecture 100%
• Lossless Compression 100%
• Computer Hardware 100%

Keyphrases

• VLSI Architecture 100%
• Viterbi Decoder 100%
• Huffman Decoder 100%
• Decoder 40%
• Communication Systems 20%
• Computational Techniques 20%
• Decomposition Method 20%
• Hardware Complexity 20%
• Speed Limit 20%
• Tree-based 20%
• Parallel Architecture 20%
• Parallel Implementation 20%
• Look-ahead Computation 20%
• Hardware Overhead 20%
• Incremental Computation 20%
• Block Implementation 20%
• Lossless Compression 20%
• High-speed Implementation 20%
• Logic Minimization 20%
• Pipelined Architecture 20%

Engineering

• Communication System 100%
• Hardware Complexity 100%
• Speed Limitation 100%
• Hardware Overhead 100%
• Lossless Compression 100%