HIGH SPEED PARALLEL ENCODER/DECODER FOR b-ADJACENT ERROR-CHECKING CODES.

Atul K. Bhatt; Larry L. Kinney

HIGH SPEED PARALLEL ENCODER/DECODER FOR b-ADJACENT ERROR-CHECKING CODES.

Atul K. Bhatt
, Larry L. Kinney

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

Codes for correction and/or detection of errors which can affect b adjacent bits in memories are considered. The class of Reed-Solomon SEC-DED codes is used. The major goal was to determine the complexity of high-speed decoders for these codes. A completely parallel (combinational logic) implementation of a (44, 32) code is given. The complexity and delay of the decoder is not impractical. The implementation is modular based on arithmetic operations over the Galois Field GF(2**b). The basic structure of the encoder/decoder is the same for other code word lengths.

Original language	English (US)
Pages	203-207
Number of pages	5
State	Published - Jan 1 2017
Event	USA - Jpn Comput Conf Proc, 3rd - San Francisco, CA, USA Duration: Oct 10 1978 → Oct 12 1978

Other

Other	USA - Jpn Comput Conf Proc, 3rd
City	San Francisco, CA, USA
Period	10/10/78 → 10/12/78

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title = "HIGH SPEED PARALLEL ENCODER/DECODER FOR b-ADJACENT ERROR-CHECKING CODES.",

abstract = "Codes for correction and/or detection of errors which can affect b adjacent bits in memories are considered. The class of Reed-Solomon SEC-DED codes is used. The major goal was to determine the complexity of high-speed decoders for these codes. A completely parallel (combinational logic) implementation of a (44, 32) code is given. The complexity and delay of the decoder is not impractical. The implementation is modular based on arithmetic operations over the Galois Field GF(2**b). The basic structure of the encoder/decoder is the same for other code word lengths.",

author = "Bhatt, \{Atul K.\} and Kinney, \{Larry L.\}",

year = "2017",

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note = "USA - Jpn Comput Conf Proc, 3rd ; Conference date: 10-10-1978 Through 12-10-1978",

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AU - Bhatt, Atul K.

AU - Kinney, Larry L.

PY - 2017/1/1

Y1 - 2017/1/1

N2 - Codes for correction and/or detection of errors which can affect b adjacent bits in memories are considered. The class of Reed-Solomon SEC-DED codes is used. The major goal was to determine the complexity of high-speed decoders for these codes. A completely parallel (combinational logic) implementation of a (44, 32) code is given. The complexity and delay of the decoder is not impractical. The implementation is modular based on arithmetic operations over the Galois Field GF(2**b). The basic structure of the encoder/decoder is the same for other code word lengths.

AB - Codes for correction and/or detection of errors which can affect b adjacent bits in memories are considered. The class of Reed-Solomon SEC-DED codes is used. The major goal was to determine the complexity of high-speed decoders for these codes. A completely parallel (combinational logic) implementation of a (44, 32) code is given. The complexity and delay of the decoder is not impractical. The implementation is modular based on arithmetic operations over the Galois Field GF(2**b). The basic structure of the encoder/decoder is the same for other code word lengths.

UR - https://www.scopus.com/pages/publications/0019340182

UR - https://www.scopus.com/pages/publications/0019340182#tab=citedBy

M3 - Paper

AN - SCOPUS:0019340182

SP - 203

EP - 207

T2 - USA - Jpn Comput Conf Proc, 3rd

Y2 - 10 October 1978 through 12 October 1978

ER -

HIGH SPEED PARALLEL ENCODER/DECODER FOR b-ADJACENT ERROR-CHECKING CODES.

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