Abstract
Codes for correction and/or detection of errors which can affect b adjacent bits in memories are considered. The class of Reed-Solomon SEC-DED codes is used. The major goal was to determine the complexity of high-speed decoders for these codes. A completely parallel (combinational logic) implementation of a (44, 32) code is given. The complexity and delay of the decoder is not impractical. The implementation is modular based on arithmetic operations over the Galois Field GF(2**b). The basic structure of the encoder/decoder is the same for other code word lengths.
| Original language | English (US) |
|---|---|
| Pages | 203-207 |
| Number of pages | 5 |
| State | Published - Jan 1 2017 |
| Event | USA - Jpn Comput Conf Proc, 3rd - San Francisco, CA, USA Duration: Oct 10 1978 → Oct 12 1978 |
Other
| Other | USA - Jpn Comput Conf Proc, 3rd |
|---|---|
| City | San Francisco, CA, USA |
| Period | 10/10/78 → 10/12/78 |