High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

Chao Cheng; Keshab K. Parhi

doi:10.1109/TCSII.2006.882213

High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

Chao Cheng, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

55 Scopus citations

Abstract

This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost.

Original language	English (US)
Pages (from-to)	1017-1021
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	53
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2006.882213
State	Published - Oct 2006

Keywords

Cyclic redundancy check (CRC)
linear feedback shift register (LFSR)
pipelining
retiming unfolding
unfolding

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10.1109/TCSII.2006.882213

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High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

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Keywords

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