High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

Chao Cheng, Keshab K. Parhi

Research output: Contribution to journalArticle

48 Scopus citations


This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost.

Original languageEnglish (US)
Pages (from-to)1017-1021
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number10
StatePublished - Oct 2006



  • Cyclic redundancy check (CRC)
  • linear feedback shift register (LFSR)
  • pipelining
  • retiming unfolding
  • unfolding

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