TY - GEN
T1 - High-speed implementation of smith-waterman algorithm for DNA sequence scanning in VLSI
AU - Cheng, Chao
AU - Parhi, Keshab K
PY - 2008/12/1
Y1 - 2008/12/1
N2 - In this paper, a novel pipelined algorithm is applied in the hardware implementation of Smith-Waterman algorithm. The proposed algorithm can cut down the computation time from O(m+n) to O(m+n/J), where J is the pipeline level, m and n are the lengths of the query sequence and subject sequence respectively. It's obvious that if the length of subject sequence is much larger than the query sequence, i.e., nm, the computation of scanning protein sequences will be speeded up by a factor of J.
AB - In this paper, a novel pipelined algorithm is applied in the hardware implementation of Smith-Waterman algorithm. The proposed algorithm can cut down the computation time from O(m+n) to O(m+n/J), where J is the pipeline level, m and n are the lengths of the query sequence and subject sequence respectively. It's obvious that if the length of subject sequence is much larger than the query sequence, i.e., nm, the computation of scanning protein sequences will be speeded up by a factor of J.
KW - DNA sequence
KW - FPGA
KW - Look-ahead pipelining
KW - Smith-Waterman Algorithm
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=70349671039&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70349671039&partnerID=8YFLogxK
U2 - 10.1109/ACSSC.2008.5074677
DO - 10.1109/ACSSC.2008.5074677
M3 - Conference contribution
AN - SCOPUS:70349671039
SN - 9781424429417
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 1528
EP - 1533
BT - 2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008
T2 - 2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008
Y2 - 26 October 2008 through 29 October 2008
ER -