High-speed CORDIC implementations using advanced circuit techniques

This paper presents results on using advanced domino circuit design techniques to implement a CORDIC processor. Skew-tolerant domino, enhanced precharged contention, non-blocking domino and pulsed reset domino circuit techniques are explained and applied to the implementation of this functional unit. For comparison purposes, a baseline design using standard two-phase domino with intermediate latches is also developed. Simulation results show that significant throughput improvement is possible using the advanced circuit techniques, with the pulsed reset style having the highest speed. On the other hand, these approaches result in increased power dissipation.