TY - JOUR

T1 - High-speed CORDIC algorithm and architecture for DSP applications

AU - Kuhlmann, Martin

AU - Parhi, Keshab K

PY - 1999/12/1

Y1 - 1999/12/1

N2 - This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or y-remainder after each iteration is no longer required. By using Most-Significant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1.5 n+2) and (1.5 n+10) full-adders (n corresponds to the word-length of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i-1 in the CORDIC rotation. Optional pipelining can lead for example to an on-line delay of three clock-cycles where every clock cycles corresponds to a delay of twelve full-adders.

AB - This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or y-remainder after each iteration is no longer required. By using Most-Significant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1.5 n+2) and (1.5 n+10) full-adders (n corresponds to the word-length of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i-1 in the CORDIC rotation. Optional pipelining can lead for example to an on-line delay of three clock-cycles where every clock cycles corresponds to a delay of twelve full-adders.

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M3 - Conference article

AN - SCOPUS:0033307426

SP - 732

EP - 741

JO - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

JF - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

SN - 1520-6130

T2 - 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation'

Y2 - 20 October 1999 through 22 October 1999

ER -