High-speed CORDIC algorithm and architecture for DSP applications

Martin Kuhlmann, Keshab K Parhi

Research output: Contribution to journalConference articlepeer-review

18 Scopus citations


This paper presents a novel CORDIC algorithm and architecture for the rotation and vectoring mode in circular coordinate systems in which the directions of all micro-rotations are precomputed while maintaining a constant scale factor. Thus, an examination of the sign of the angle or y-remainder after each iteration is no longer required. By using Most-Significant Digit (MSD) first adder/multiplier, the critical path of the entire CORDIC architecture only requires (1.5 n+2) and (1.5 n+10) full-adders (n corresponds to the word-length of the inputs) for rotation and vectoring modes, respectively. This is a speed improvement of about 30% compared to the previously fastest reported shared rotation and vectoring mode implementations. Additionally, there is a higher degree of freedom in choosing the pipeline cutsets due to the novel independence of iteration i and i-1 in the CORDIC rotation. Optional pipelining can lead for example to an on-line delay of three clock-cycles where every clock cycles corresponds to a delay of twelve full-adders.

Original languageEnglish (US)
Pages (from-to)732-741
Number of pages10
JournalIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
StatePublished - Dec 1 1999
Event1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan
Duration: Oct 20 1999Oct 22 1999


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