TY - JOUR
T1 - High-speed circuits for a multi-lane 12 Gbps CMOS PRBS generator
AU - Bommalingaiahnapallya, Shubha
AU - Sham, Kin Joe
AU - Ahmadi, Mahmoud Reza
AU - Harjani, Ramesh
PY - 2007
Y1 - 2007
N2 - This paper presents the design of a 12 Gbps multilane 231 -1 pseudo-random binary sequence (PRBS) generator in 0.18 μm TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to the fT of the process. In order to operate at frequencies higher than the limit imposed by the fT of the PMOS devices, the PRBS uses current-mode logic (CML) multiplexers (MUX) with modified active inductors, resulting in an improved large-signal behavior. As the architecture of choice for the PRBS generator, we chose to generate four sub-sequences at 3 Gbps and multiplex them up to obtain a 12 Gbps data stream. Furthermore, we multiplexed delayed versions of the 3 Gbps sub-sequences to obtain multiple non-correlated versions of the 231 - 1 pseudo-random sequence,. A prototype was implemented in 0.18 μm TSMC process. The high-speed CML MUX consumes 4 mA off a 1.8 V power supply, while the CMOS latch clocked at 1.5 GHz with an activity factor of 100% consumes 1 mA. The CMOS core consumes 340 mA and the CML circuitry consumes 32 mA per lane.
AB - This paper presents the design of a 12 Gbps multilane 231 -1 pseudo-random binary sequence (PRBS) generator in 0.18 μm TSMC process. The design incorporates a traditional CMOS latch optimized to operate at frequencies close to the fT of the process. In order to operate at frequencies higher than the limit imposed by the fT of the PMOS devices, the PRBS uses current-mode logic (CML) multiplexers (MUX) with modified active inductors, resulting in an improved large-signal behavior. As the architecture of choice for the PRBS generator, we chose to generate four sub-sequences at 3 Gbps and multiplex them up to obtain a 12 Gbps data stream. Furthermore, we multiplexed delayed versions of the 3 Gbps sub-sequences to obtain multiple non-correlated versions of the 231 - 1 pseudo-random sequence,. A prototype was implemented in 0.18 μm TSMC process. The high-speed CML MUX consumes 4 mA off a 1.8 V power supply, while the CMOS latch clocked at 1.5 GHz with an activity factor of 100% consumes 1 mA. The CMOS core consumes 340 mA and the CML circuitry consumes 32 mA per lane.
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U2 - 10.1109/iscas.2007.377890
DO - 10.1109/iscas.2007.377890
M3 - Conference article
AN - SCOPUS:34548858980
SN - 0271-4310
SP - 3896
EP - 3899
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 4253533
T2 - 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
Y2 - 27 May 2007 through 30 May 2007
ER -