High-speed architectures for parallel long BCH encoders

Xinmiao Zhang, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations


Long BCH codes are used as the outer error-correcting code in the second generation of Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6dB additional coding gain over Reed-Solomon codes with similar codeword length and code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. High-speed applications of BCH codes require parallel implementations of encoders. In addition, long BCH encoders suffer from the effect of large fanout. In this paper, novel architectures are proposed to reduce the achievable minimum clock period of long BCH encoders after the fanout bottleneck has been eliminated. For an (8191, 7684) BCH code, compared to the original 32-parallel BCH encoder architecture without fanout bottleneck, the proposed architectures can achieve a speedup of over 100%.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publicationVLSI in the Nanometer Era
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
ISBN (Print)1581138539, 9781581138535
StatePublished - 2004
EventProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
Duration: Apr 26 2004Apr 28 2004

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI


OtherProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country/TerritoryUnited States
CityBoston, MA


  • BCH
  • Critical loop
  • Encoder
  • Fanout
  • Generator polynomial
  • Iteration bound
  • Linear feedback shift register
  • Parallel processing
  • Retiming
  • Un-folding


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