Abstract
Concurrent fine-grain pipelined VLSI architectures for dynamic programming (DP) problems are presented. Look-ahead is used to obtain finer-grain pipelining, and a novel precomputation sequence is used to design DP computation architectures with square to linear add-compare-select (ACS) processor complexity (in number of states in the DP problem). Use of nonuniform pipelining and nonuniform implementation methodologies in dedicated DP architectures is introduced; this results in a saving of hardware modules with no loss in speed. A two's complement least-significant-bit-first bit-serial architecture is also presented for the compare-select operation.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1041-1044 |
| Number of pages | 4 |
| Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
| Volume | 2 |
| State | Published - Dec 1 1990 |
| Event | 1990 International Conference on Acoustics, Speech, and Signal Processing: Speech Processing 2, VLSI, Audio and Electroacoustics Part 2 (of 5) - Albuquerque, New Mexico, USA Duration: Apr 3 1990 → Apr 6 1990 |
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High-speed architectures for dynamic programming problems. / Parhi, Keshab K.
In: ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, Vol. 2, 01.12.1990, p. 1041-1044.Research output: Contribution to journal › Conference article
}
TY - JOUR
T1 - High-speed architectures for dynamic programming problems
AU - Parhi, Keshab K
PY - 1990/12/1
Y1 - 1990/12/1
N2 - Concurrent fine-grain pipelined VLSI architectures for dynamic programming (DP) problems are presented. Look-ahead is used to obtain finer-grain pipelining, and a novel precomputation sequence is used to design DP computation architectures with square to linear add-compare-select (ACS) processor complexity (in number of states in the DP problem). Use of nonuniform pipelining and nonuniform implementation methodologies in dedicated DP architectures is introduced; this results in a saving of hardware modules with no loss in speed. A two's complement least-significant-bit-first bit-serial architecture is also presented for the compare-select operation.
AB - Concurrent fine-grain pipelined VLSI architectures for dynamic programming (DP) problems are presented. Look-ahead is used to obtain finer-grain pipelining, and a novel precomputation sequence is used to design DP computation architectures with square to linear add-compare-select (ACS) processor complexity (in number of states in the DP problem). Use of nonuniform pipelining and nonuniform implementation methodologies in dedicated DP architectures is introduced; this results in a saving of hardware modules with no loss in speed. A two's complement least-significant-bit-first bit-serial architecture is also presented for the compare-select operation.
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UR - http://www.scopus.com/inward/citedby.url?scp=0025670798&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0025670798
VL - 2
SP - 1041
EP - 1044
JO - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
JF - Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
SN - 0736-7791
ER -