High-speed architectures for dynamic programming problems

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Abstract

Concurrent fine-grain pipelined VLSI architectures for dynamic programming (DP) problems are presented. Look-ahead is used to obtain finer-grain pipelining, and a novel precomputation sequence is used to design DP computation architectures with square to linear add-compare-select (ACS) processor complexity (in number of states in the DP problem). Use of nonuniform pipelining and nonuniform implementation methodologies in dedicated DP architectures is introduced; this results in a saving of hardware modules with no loss in speed. A two's complement least-significant-bit-first bit-serial architecture is also presented for the compare-select operation.

Original languageEnglish (US)
Pages (from-to)1041-1044
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume2
StatePublished - Dec 1 1990

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dynamic programming
Dynamic programming
high speed
very large scale integration
complement
central processing units
hardware
modules
methodology
Hardware

Cite this

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