High speed algorithm and VLSI architecture design for decoding BCH product codes

Keyphrases

• VLSI Architecture Design 100%
• Algorithm Architecture 100%
• Product Codes 100%
• Design Strategy 50%
• High-order 50%
• Two Dimensional 50%
• Bit Error Rate 50%
• Signal-to-noise Ratio 50%
• Turbo Codes 50%
• CMOS Technology 50%
• VLSI Implementation 50%
• Area Consumption 50%
• 6-bit 50%
• Top Level 50%
• Parallel Decoding 50%
• Decoding Throughput 50%
• Logic Synthesis 50%
• High-speed Implementation 50%
• Suboptimal Algorithms 50%
• Finite Wordlength Effect 50%
• SISO Decoder 50%
• Finite Field Operations 50%
• VLSI Decoder Architectures 50%
• Full Parallel 50%
• Merge Sort 50%
• Block Turbo Code 50%
• Turbo Product Codes 50%

Engineering

• Product Code 100%
• Two Dimensional 33%
• Signal-to-Noise Ratio 33%
• Field Operation 33%
• Logic Synthesis 33%
• Bit Error Rate 33%
• Critical Path 33%