This paper presents a novel application of skew-tolerant domino circuit design by combining the effects of time borrowing and early carry propagation in a 64-bit adder. Skew-tolerant circuit design softens the clock edges and allows time borrowing from one stage of logic to the next in a pipeline. Early carry propagation also softens clock edges by allowing useful work to be done during the precharge phase. In this paper, these two effects are used simultaneously, resulting in a significant reduction in latency. Simulation results show that up to a 42% decrease in delay can be achieved over a traditional two-phase clocking design when both techniques are combined in the same circuit.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - Jan 1 2000|