High-speed add-compare-select units using locally self-resetting CMOS

Gunok Jung; Jun Jin Kong; Gerald E Sobelman; Keshab K Parhi

doi:10.1109/ISCAS.2002.1009984

High-speed add-compare-select units using locally self-resetting CMOS

Gunok Jung, Jun Jin Kong, Gerald E Sobelman, Keshab K Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

This paper presents a new self-resetting CMOS design for an Add-Compare-Select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.

Original language	English (US)
Pages (from-to)	889-892
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.2002.1009984
State	Published - 2002

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10.1109/ISCAS.2002.1009984

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abstract = "This paper presents a new self-resetting CMOS design for an Add-Compare-Select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.",

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AU - Sobelman, Gerald E

AU - Parhi, Keshab K

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AB - This paper presents a new self-resetting CMOS design for an Add-Compare-Select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.

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ER -

High-speed add-compare-select units using locally self-resetting CMOS

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