High-speed add-compare-select units using locally self-resetting CMOS

Gunok Jung, Jun Jin Kong, Gerald E Sobelman, Keshab K Parhi

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This paper presents a new self-resetting CMOS design for an Add-Compare-Select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMOS designs have also been implemented for comparison purposes. The simulation results show that, with the SRCMOS technique, the ACS units operate at a data rate of 568 Mbps in a 0.25 micron CMOS technology, as compared to 357 Mbps and 485 Mbps for static and domino CMOS implementations, respectively.

Original languageEnglish (US)
Pages (from-to)889-892
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 2002

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