Abstract
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of recent techniques for the analysis and optimization of supply networks, and discusses future trends in power grid design.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 839-844 |
| Number of pages | 6 |
| Journal | Proceedings of the IEEE International Conference on VLSI Design |
| Volume | 17 |
| State | Published - 2004 |
| Event | Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India Duration: Jan 5 2004 → Jan 9 2004 |
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