High-performance power grids for nanometer technologies

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations


With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of recent techniques for the analysis and optimization of supply networks, and discusses future trends in power grid design.

Original languageEnglish (US)
Pages (from-to)839-844
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
StatePublished - May 24 2004
EventProceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design - Mumbai, India
Duration: Jan 5 2004Jan 9 2004


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