High-performance digit-serial complex-number multiplier-accumulator

Yun Nan Chang, Keshab K Parhi

Research output: Contribution to conferencePaperpeer-review

9 Scopus citations

Abstract

This paper presents a fast highly regular digit-serial complex-number multiplier-accumulator (CMAC) architecture which is well suited for VLSI implementations. This paper makes two contributions. First, several complex-number representation schemes are discussed. It is shown that the real-imaginary alternate (RIA) scheme is the best among all representation schemes and the prior designs of CMACs based on the radix-(2j) Redundant Complex Number System (RCNS) are not efficient with respect to hardware complexity and processing speed. Second, digit-serial CMAC architectures which can be pipelined at fine-grain level to increase the throughput rate are designed based on carry-save configuration.

Original languageEnglish (US)
Pages211-213
Number of pages3
StatePublished - Dec 1 1998
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: Oct 5 1998Oct 7 1998

Other

OtherProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period10/5/9810/7/98

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