Abstract
This paper presents a fast highly regular digit-serial complex-number multiplier-accumulator (CMAC) architecture which is well suited for VLSI implementations. This paper makes two contributions. First, several complex-number representation schemes are discussed. It is shown that the real-imaginary alternate (RIA) scheme is the best among all representation schemes and the prior designs of CMACs based on the radix-(2j) Redundant Complex Number System (RCNS) are not efficient with respect to hardware complexity and processing speed. Second, digit-serial CMAC architectures which can be pipelined at fine-grain level to increase the throughput rate are designed based on carry-save configuration.
| Original language | English (US) |
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| Pages | 211-213 |
| Number of pages | 3 |
| State | Published - Dec 1 1998 |
| Event | Proceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA Duration: Oct 5 1998 → Oct 7 1998 |
Other
| Other | Proceedings of the 1998 IEEE International Conference on Computer Design |
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| City | Austin, TX, USA |
| Period | 10/5/98 → 10/7/98 |