Abstract
This brief presents a fast highly regular digit-serial complex multiplier (CMUL) architecture which is well suited for VLSI implementations. This brief makes two contributions. First, several complex-number representation schemes are discussed. It is shown that the proposed real-imaginary alternate scheme is the best among all representation schemes and the prior designs of CMUL's based on the radix-(2j) Redundant Complex Number System (RCNS) are not efficient with respect to hardware complexity and processing speed. Second, digit-serial CMUL architectures which can be pipelined at fine-grain level to increase the throughput rate are designed based on carry-save configuration. The proposed design methodology can also result in low-power dissipation due to the reduced wiring complexity and glitching activity.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 570-572 |
| Number of pages | 3 |
| Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
| Volume | 47 |
| Issue number | 6 |
| DOIs | |
| State | Published - 2000 |
Bibliographical note
Funding Information:Manuscript received July 1999; revised February 2000. This research was supported by Defense Advanced Research Project Agency under Contract DA/DABT63-96-C-0050. This paper was recommended by Associate Editor E. Friedman. Y.-N. Chang is with the Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi 621, Taiwan, R.O.C. K. K. Parhi is with the Department of Electrical and Computer Engineering, University of Minnesota, MN 55455 USA. Publisher Item Identifier S 1057-7130(00)04982-X.