High performance CMOS macromodule layout synthesis

Jaewon Kim, S. M. Kang, Sachin S. Sapatnekar

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

A new high-performance CMOS macromodule layout synthesis system is presented. The layout is based on a new flexible logic cell array platform and channelless routing with compaction, utilizing three layers of metallic interconnects. The flexible cells are placed into rows whose heights can be customized to minimize the total area, while meeting the user-specified aspect ratio of the macromodule. The triple metal layer channelless routing problem with irregular boundaries is mapped to the composite problem of channelless two-layer routing and segment squeezing with layer conversion. To meet the user-specified specifications on circuit delays, in addition to well-established placement and routing, a rigorous transistor sizing program, which employs convex programming techniques, is used to find the minimum active area that satisfies all the delay specifications. The optimal transistor sizes are then implemented in the flexible cell and a new layout is generated. This process is iterated until the layout meets all the timing requirements.

Original languageEnglish (US)
Pages (from-to)179-182
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Dec 1 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

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