The rapidly growing wireless communication industry is increasingly demanding CMOS RF ICs due to their lower costs and higher integration levels. The RF front-end of such wireless systems often needs to handle widely disparate signal levels: small desired signals and large interferers. Therefore, it becomes necessary to have highly linear circuits to increase the system dynamic range. However, traditional CMOS circuit designs are usually limited in either their speed or in their linear performance. New techniques are needed to meet the demand for high linearity at radio frequencies. High-Linearity CMOS RF Front-End Circuits presents some unique techniques to enhance the linearity of both the receiver and transmitter. For example, using harmonic cancellation techniques, the linearity of the receiver front-end can be increased by few tens of dB with only minimal impact on the other circuit parameters. The new parallel class A&B power amplifier can not only increase the transmitter's output power in the linear range, but can also result in significant savings in power consumption. High-Linearity CMOS RF Front-End Circuits can be used as a textbook for graduate courses in RF CMOS design and will also be useful as a reference for the practicing engineer.