In this paper we address methodologies for high-level synthesis of dedicated digital signal processing (DSP) architectures using the Minesota ARchitecture Synthesis (MARS) design system. We present new concurrent scheduling and resource allocation algorithms which exploit interiteration and intra-iteration precedence constraints. These novel algorithms produce solutions which are as good as or better than those previously published. Previous synthesis systems have focused on DSP algorithms which have single or lumped delays in the recursive loops. MARS is capable of generating valid architectures for algorithms which have distributed arc delays arid exploits these delays to produce more efficient architectures. This allows our system to be more general and provides for the synthesis of more complicated algorithms. Our system utilizes implicit retiming and pipelining of the data flow graph to improve the quality of the design. We are able to synthesize architectures which meet the iteration bound of any algorithm by unfolding the original data flow graph.
|Original language||English (US)|
|Title of host publication||1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - 1992|
|Event||1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States|
Duration: May 10 1992 → May 13 1992
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992|
|Period||5/10/92 → 5/13/92|
Bibliographical noteFunding Information:
This research was supported in puts by Texas Instruments, the office of Naval Research under contract number N00014-9I-J-I008, and the Army Research Office under contract number DAAL03-90-G-0063.
© 1992 IEEE.
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