High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

Mark J. Mercer, Stanley G. Burns

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 fT transistors.

Original languageEnglish (US)
Pages (from-to)3225-3229
Number of pages5
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Dec 1 1990
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: May 1 1990May 3 1990

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