Abstract
The author describes analog circuit design methodologies and techniques required to optimize high frequency performance when operating near the upper frequency limit of BJT-based analog ASICs. The Tektronix QuickChip 2S ASIC array is used as the analysis and test vehicle. These techniques are illustrated using a series of examples including an actively shunt-peaked wideband amplifier and a multi-chip FM receiver as well as an analysis of the need to optimize the RC product in the manual routing of both metallizations in critical areas of the circuit.
Original language | English (US) |
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Title of host publication | Proceedings - 1st Great Lakes Symposium on VLSI, GLSV 1991 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 196-201 |
Number of pages | 6 |
ISBN (Electronic) | 0818621702, 9780818621703 |
DOIs | |
State | Published - 1991 |
Externally published | Yes |
Event | 1st Great Lakes Symposium on VLSI, GLSV 1991 - Kalamazoo, United States Duration: Mar 1 1991 → Mar 2 1991 |
Publication series
Name | Proceedings - 1st Great Lakes Symposium on VLSI, GLSV 1991 |
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Conference
Conference | 1st Great Lakes Symposium on VLSI, GLSV 1991 |
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Country/Territory | United States |
City | Kalamazoo |
Period | 3/1/91 → 3/2/91 |
Bibliographical note
Publisher Copyright:© 1991 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.