Abstract
This paper presents a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described and then extended to multi-level and "virtual-layer" hierarchy. Experimental results show that these algorithms not only achieve speedups over the generic random-walk method, but also are more robust in solving various types of industrial circuits. For example, a 71K-node circuit is solved in 4.16 seconds, showing a more than 4 times speedup over the generic method; a 348K-node wire-bond power grid, for which the performance of the generic method degrades, is solved in 75.88 seconds.
| Original language | English (US) |
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| Pages | 499-504 |
| Number of pages | 6 |
| DOIs | |
| State | Published - 2004 |
| Event | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: Jan 27 2004 → Jan 30 2004 |
Other
| Other | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 |
|---|---|
| Country/Territory | Japan |
| City | Yokohama |
| Period | 1/27/04 → 1/30/04 |