A novel approach for hierarchically pipelining and folding the CORDIC-based systolic triangular array of a QRD-RLS filter to a small fixed size array is presented. With the annihilation-reordering look-ahead transformation, the iteration bound of a QRD-RLS filter can be reduced proportional to the look-ahead level. This paper presents, for the first time, how to pipeline and fold such a look-ahead transformed QRD-RLS array in a hierarchical way. Compared to the previously published mapping algorithms, this approach has low complexity and can result in a physical array of any size. Therefore, it is of great significance for ASIC chip designs and high-level synthesis. Besides, it is shown how a combination of look-ahead, pipelining and folding transformations can lead to an increase in throughput, a large reduction in area or a great saving in power consumption.