Hierarchical folding and synthesis of iterative data flow graphs

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Abstract

Folding transformation enables synthesis of digital signal processing algorithms described by iterative data flow graphs (DFGs). For a specified feasible folding set, it returns a synthesized hardware architecture described by a hardware DFG. This brief presents hierarchical folding and hierarchical synthesis of iterative DFGs that contain many identical or similar substructures. Instead of performing folding or synthesis on the entire large DFG, the hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by appropriately changing the number of delays and switch instances in this folded structure. The advantage lies in significant reduction in execution time. Two different approaches to hierarchical folding presented include hierarchical interleaved folding and hierarchical contiguous folding. Experimental results show that the run time increase of the synthesis process for a 20-cascaded fifth-order wave digital filter can be reduced from 2000% to 30% using hierarchical synthesis instead of conventional synthesis, compared with the run time for synthesis of one section.

Original languageEnglish (US)
Pages (from-to)597-601
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume60
Issue number9
DOIs
StatePublished - Jul 18 2013

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Keywords

  • Folding
  • hierarchical folding
  • hierarchical synthesis
  • interleaving
  • iterative data flow graphs (DFGs)
  • time-multiplexed circuit synthesis

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