Hierarchical folding and synthesis of iterative data flow graphs

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Folding transformation enables synthesis of digital signal processing algorithms described by iterative data flow graphs (DFGs). For a specified feasible folding set, it returns a synthesized hardware architecture described by a hardware DFG. This brief presents hierarchical folding and hierarchical synthesis of iterative DFGs that contain many identical or similar substructures. Instead of performing folding or synthesis on the entire large DFG, the hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by appropriately changing the number of delays and switch instances in this folded structure. The advantage lies in significant reduction in execution time. Two different approaches to hierarchical folding presented include hierarchical interleaved folding and hierarchical contiguous folding. Experimental results show that the run time increase of the synthesis process for a 20-cascaded fifth-order wave digital filter can be reduced from 2000% to 30% using hierarchical synthesis instead of conventional synthesis, compared with the run time for synthesis of one section.

Original languageEnglish (US)
Pages (from-to)597-601
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume60
Issue number9
DOIs
StatePublished - Jul 18 2013

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Data flow graphs
Hardware
Digital filters
Digital signal processing
Switches

Keywords

  • Folding
  • hierarchical folding
  • hierarchical synthesis
  • interleaving
  • iterative data flow graphs (DFGs)
  • time-multiplexed circuit synthesis

Cite this

Hierarchical folding and synthesis of iterative data flow graphs. / Parhi, Keshab K.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, No. 9, 18.07.2013, p. 597-601.

Research output: Contribution to journalArticle

@article{70001bed2023403a8a1502130369183c,
title = "Hierarchical folding and synthesis of iterative data flow graphs",
abstract = "Folding transformation enables synthesis of digital signal processing algorithms described by iterative data flow graphs (DFGs). For a specified feasible folding set, it returns a synthesized hardware architecture described by a hardware DFG. This brief presents hierarchical folding and hierarchical synthesis of iterative DFGs that contain many identical or similar substructures. Instead of performing folding or synthesis on the entire large DFG, the hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by appropriately changing the number of delays and switch instances in this folded structure. The advantage lies in significant reduction in execution time. Two different approaches to hierarchical folding presented include hierarchical interleaved folding and hierarchical contiguous folding. Experimental results show that the run time increase of the synthesis process for a 20-cascaded fifth-order wave digital filter can be reduced from 2000{\%} to 30{\%} using hierarchical synthesis instead of conventional synthesis, compared with the run time for synthesis of one section.",
keywords = "Folding, hierarchical folding, hierarchical synthesis, interleaving, iterative data flow graphs (DFGs), time-multiplexed circuit synthesis",
author = "Parhi, {Keshab K}",
year = "2013",
month = "7",
day = "18",
doi = "10.1109/TCSII.2013.2268658",
language = "English (US)",
volume = "60",
pages = "597--601",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

TY - JOUR

T1 - Hierarchical folding and synthesis of iterative data flow graphs

AU - Parhi, Keshab K

PY - 2013/7/18

Y1 - 2013/7/18

N2 - Folding transformation enables synthesis of digital signal processing algorithms described by iterative data flow graphs (DFGs). For a specified feasible folding set, it returns a synthesized hardware architecture described by a hardware DFG. This brief presents hierarchical folding and hierarchical synthesis of iterative DFGs that contain many identical or similar substructures. Instead of performing folding or synthesis on the entire large DFG, the hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by appropriately changing the number of delays and switch instances in this folded structure. The advantage lies in significant reduction in execution time. Two different approaches to hierarchical folding presented include hierarchical interleaved folding and hierarchical contiguous folding. Experimental results show that the run time increase of the synthesis process for a 20-cascaded fifth-order wave digital filter can be reduced from 2000% to 30% using hierarchical synthesis instead of conventional synthesis, compared with the run time for synthesis of one section.

AB - Folding transformation enables synthesis of digital signal processing algorithms described by iterative data flow graphs (DFGs). For a specified feasible folding set, it returns a synthesized hardware architecture described by a hardware DFG. This brief presents hierarchical folding and hierarchical synthesis of iterative DFGs that contain many identical or similar substructures. Instead of performing folding or synthesis on the entire large DFG, the hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by appropriately changing the number of delays and switch instances in this folded structure. The advantage lies in significant reduction in execution time. Two different approaches to hierarchical folding presented include hierarchical interleaved folding and hierarchical contiguous folding. Experimental results show that the run time increase of the synthesis process for a 20-cascaded fifth-order wave digital filter can be reduced from 2000% to 30% using hierarchical synthesis instead of conventional synthesis, compared with the run time for synthesis of one section.

KW - Folding

KW - hierarchical folding

KW - hierarchical synthesis

KW - interleaving

KW - iterative data flow graphs (DFGs)

KW - time-multiplexed circuit synthesis

UR - http://www.scopus.com/inward/record.url?scp=84884590752&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84884590752&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2013.2268658

DO - 10.1109/TCSII.2013.2268658

M3 - Article

VL - 60

SP - 597

EP - 601

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-8328

IS - 9

ER -