Hierarchical approach to transistor-level power estimation of arithmetic units

Janardhan H. Satyanarayana, Keshab K Parhi

Research output: Contribution to journalConference articlepeer-review


This paper presents an algorithm for power estimation in digital circuits using a hierarchical approach. The salient feature of this approach is that it can be used to estimate the power of large digital circuits in a reasonably short time. Moreover, it takes into account both the spatial correlations introduced in the circuit due to reconvergent fanout, and the delays associated with the various computation units. Here, the circuit is partitioned into sub-circuits which are modeled using state transition diagrams (stds), and the energy, and therefore power, associated with the circuit is then computed from its constituent stds by treating them as irreducible Markov chains. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations. However, the computation time required by the proposed approach is orders of magnitude less than that required by SPICE.

Original languageEnglish (US)
Pages (from-to)3338-3341
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
StatePublished - 1996
EventProceedings of the 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP. Part 1 (of 6) - Atlanta, GA, USA
Duration: May 7 1996May 10 1996


Dive into the research topics of 'Hierarchical approach to transistor-level power estimation of arithmetic units'. Together they form a unique fingerprint.

Cite this