Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units

Yun Nan Chang, Ching Y.I. Wang, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume that a library of functional units based on heterogeneous implementation style is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

Original languageEnglish (US)
Pages (from-to)243-256
Number of pages14
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Issue number3
StatePublished - 1998

Bibliographical note

Funding Information:
This research was supported by the Advanced Research Projects Agency and the Solid State Electronics Directorate, Wright-Patterson AFB under contract number AF/F33615-93-C-1309.


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