### Abstract

This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume that a library of functional units based on heterogeneous implementation style is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

Original language | English (US) |
---|---|

Pages (from-to) | 243-256 |

Number of pages | 14 |

Journal | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |

Volume | 19 |

Issue number | 3 |

State | Published - Dec 1 1998 |

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### Cite this

*Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology*,

*19*(3), 243-256.

**Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.** / Chang, Yun Nan; Wang, Ching Y.I.; Parhi, Keshab K.

Research output: Contribution to journal › Article

*Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology*, vol. 19, no. 3, pp. 243-256.

}

TY - JOUR

T1 - Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units

AU - Chang, Yun Nan

AU - Wang, Ching Y.I.

AU - Parhi, Keshab K

PY - 1998/12/1

Y1 - 1998/12/1

N2 - This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume that a library of functional units based on heterogeneous implementation style is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

AB - This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume that a library of functional units based on heterogeneous implementation style is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

UR - http://www.scopus.com/inward/record.url?scp=0032141050&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032141050&partnerID=8YFLogxK

M3 - Article

VL - 19

SP - 243

EP - 256

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 3

ER -