HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS with High-Speed Fixed-Point Approximation

Homomorphic encryption enables computations over ciphertext to preserve data privacy, but it introduces significant computational overhead compared to plaintext operations. In response to this challenge, we present HEDWIG, a novel end-to-end hardware acceleration system designed to enhance the efficiency of homomorphic encryption, specifically tailored for the latest BFV (Brakerski/Fan-Vercauteren)-HPS (Halevi-Polyakov-Shoup) scheme. The proposed hardware accelerator targets the BFV-HPS scheme variant and improves efficiency through three key innovations: fixed-point approximation techniques for performing floating-point operations, resource-efficient modular multipliers and unified butterfly modules, and a novel relinearization approach to reduce computational overhead. By disentangling butterfly operations from modular computations, we further minimize data dependencies and improve parallelism. The proposed HEDWIG is employed to perform homomorphic evaluations over machine learning model inference. We implement our architecture on an Xilinx U280 FPGA with a 65% reduction in DSP usage compared to the prior BFV RNS FPGA accelerator. HEDWIG only requires 5.29 ms to complete one round of BFV-HPS homomorphic multiplication in 300 MHz clock frequency.